Jointwave Professional ASIC & FPGA IP Provider
Home Products Downloads Demos News Contact us	Products Since the inception, Jointwave has been focusing on video processing and codec IP design for ASIC and FPGA. All the IP cores are provided by subsequent parts: Synthesizable verilog source files Verilog testbenches Testing scripts (shell-script, tcl and perl) C-model source files Synthesizing scripts Design and implementation documents All the IP Cores are easy to be customized and easy to be integrated into SOC. We provide comprehensive consultancy and technical support to help customers to evaluate and implement the H.264 encoder IP cores into large scale SOC.   H.264 Real-time Main Profile Encoder IP Cores Product ID E640   E660   Max Video resolution 1280x720@60fps 1920x1088@30fps 1600x1200 30fps 1920x1088 60fps 1600x1200@60fps Integrated SD/DDR(2) controller   Optional Share SD/DDR(2) controller through OCP   Optional External SD/DDR data width   16 or 32bits   32 bits Frequency (1) (MHz) 108~152 216~304 On-chip RAM (kbits) 190 190     H.264 Real-time Baseline Profile Encoder IP Cores Product ID E540 E440 E560 E460 Max Video resolution 1280x720@60fps 1920x1088@30fps 1600x1200 30fps 1920x1088 60fps 1600x1200@30fps Integrated SD/DDR(2) controller   Optional Share SD/DDR(2) controller through OCP   Optional External SD/DDR data width   16 or 32bits   32 bits Frequency (1) (MHz) 108~152 216~304 On-chip RAM (kbits) 185 185   H.264 Real-time High Profile Encoder IP Cores Product ID E740   E760   Max Video resolution 1280x720@60fps 1920x1088@30fps 1600x1200 30fps 1920x1088 60fps 1600x1200@30fps Integrated SD/DDR(2) controller   Optional Share SD/DDR(2) controller through OCP   Optional External SD/DDR data width   16 or 32bits   32 bits Frequency (1) (MHz) 108~152 216~304 On-chip RAM (kbits) 220 220   (1) Frequency listed here is the lowest frequency required. The IP core may able to run in a higher frequency. e.g. E600 is able to run from 25 MHz to 66 MHz. There are two situations the IP core can run in a higher frequency: Get a better video quality due to the enlarged searching area Synchronize with other parts of the same SOC (2) E4X0 occupies few logic gates than corresponding E5X0 encoder.   Key Feathers of H.264 Encoder IP Cores The goal of our design is to achieve outstanding video quality by relatively small logic gates and minimal low power consumption. Full searching algorithm in both full pixel and 1/4 sub-pixel motion estimation, to get best objective and subjective video quality Bit rate is 40% of MPEG2 for equal quality Configurable search range Horizontal : +/-61.75 ~ +/-21.75, Vertical : +/-29.75 ~ +/-16.75. Multiple reference frames (maximum 2) Skip mode for P frame, Direct8x8 and Direct16x16 for B frame Multiple inter prediction modes: 16x16, 16x8, 8x16, 8x8 I16x16 and I4x4 all intra prediction modes Configurable GOP pattern: I only, IPP…, IBPBP…, IBBPBBP.... Configurable GOP sequence length Exceedingly fast CABAC module, encodes 1 binarized bit per cycle. Capable of outputting 100Mbps when run at 300MHz VBR and CBR, rate control for both CAVLC and CABAC Real-time encoding, Very low latency 1/4 sub-pixel motion estimation Mode decision in 1/4 sub-pixel to get best quality Hadamard transform for both intra and inter prediction Deblocking filter Integrated SD/DDR controller, or shares SD/DDR through AHB with CPU and other parts on SOC Standalone solution, no extra CPU or software required Fully synthesizable, gate level simulation verified FPGA Proven One 1920x1088@30~60fps or 6~12 D1 high quality H.264 encoders can be put in one FPGA Maximum 600Mhz on 90nm process Maximum 480Mhz on 130nm process Maximum 300Mhz on high-end FPGA, e.g. StratixIIII, Virtex5 Maximum 1080p@60fps on Virtex5 and StratixIIII Ultra low power consumption, 82mw for 1080p@60fps on 45nm process, 98mw for 1080p@30fps on 90nm process, 20mw for 720p@30fps on 65nm process   Copyright 2009-2012 Jointwave LLC. All Rights Reserved.